8.1 Introduction

In semiconductor manufacturing, i.e. the production of integrated electronic circuits, many crucial process steps are based on vacuum technology. There are several reasons for the use of vacuum technology in Silicon processing:

  • Vacuum allows controlled conditions as it excludes the ambient atmosphere from the silicon wafer, namely reactive gases and dust.
  • Vacuum allows anisotropic etching of silicon and silicon oxide, the basic process steps for patterning the surface of the silicon wafer.
  • Several vacuum based processes allow the deposition of thin layers of all types of insulation and conducting films with controllable properties on silicon wafers.

The development of integrated circuits made from solid silicon is characterized by a steady increase of performance due to an ever increasing number of integrated components per device and shrinkage of the pattern size. In the course of his development the performance of the circuits has doubled approximately every two years since the 1960s which has been predicted by Gordon E. Moore and is known as Moore’s law [35]. This has been achieved by a reduction of the smallest structures of integrated circuits like microprocessors and random access memory from about 10 µm in 1970 to sub 0.1 µm after the turn of the millennium. During this period the size of the silicon wafers increased from 1" diameter to 300 mm (~12") to improve throughput and reduce cost.

Moore’s Law (documented by the number of
					transistors in Intel and AMD microprocessors)

Figure 8.1: Moore’s Law (documented by the number of transistors in Intel and AMD microprocessors)

With the introduction of the 300 mm technology the so called critical dimensions shrank from 150 nm and have reached 22 nm at the time this text is written (2012). With 300 mm wafer size the production technology also changed from open cassettes (Figure 8.2 left) to closed mini environment, i.e. the wafers are transferred from one process equipment to another inside the production site in closed boxes (FOUP = Front Opening Unified Pod, Figure 8.2 right).

Wafer handling with cassettes (left) and
			FOUPs (right)

Figure 8.2: Wafer handling with cassettes (left) and FOUPs (right)